By Marwan A. Jabri
In 1984, whereas i used to be following his postgraduate path on VLSI layout, my manager Dr. David Skellern, requested me if i used to be drawn to investigating clever methods to computerized Ie floorplanning. He informed me then: "a circuit that works continuously appears great, has a smart information and regulate circulate. a quick approach to examine scholars' Ie tasks is through taking a look at their fioorplans.". Later, I took a path on wisdom Engineering (KE) and synthetic Intelligence (AI) with Professor John Gero, who inspired me to enquire this sector of layout automation. The assets for such improvement have been relatively bad at IS&E as KE was once a comparatively new box of study in Australia at the moment. \'Vhatever the problems (a stable programmmer by no means blames his instruments as David Skellern used to inform me), I undertook the research of Knowledge-Based methods to Ie ftoor making plans as my PhD thesis topic with the aid of my manager and John Gero and the encouragement of all researchers at IS&E , who supplied a thrilling atmosphere for my learn. This quantity reviews the result of my examine in the course of 1984, 1985, 1986, and 1987. The voulme bargains with Ie ftoorplanning from 4 views: floorplanning method, wisdom Engineering within the Ie area, the improvement of knowledge-based fioorplan ning techniques and new floorplanning algorithms to be used within the total strategy.
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Additional info for An Artificial Intelligence Approach to Integrated Circuit Floorplanning
2 The PIAF Modular Architecture We present in the following paragraphs an overview of the architecture of PIAF. The following three chapters present in detail the implementation of the different components. 44 The KBS PIF is the top level component of PIAF. It manages the fioorplanning strategy, and supports other tasks such as the acquisition of the input circuit through the FBD graphic editor. PIF manipulates a wide range of objects and attributes which are generally subject to transformation through the applications of rules or algorithms.
The equations and the constraints are input to Simplex algorithms where the cost equations are the total width and total height of the chip. The outputs of the algorithms are the width and height of the blocks that satisfy the constraints and minimise the total width and total height of the chip. Phase 4: Determination of the Satisfying Area With the block shapes found, minimal block areas (the weight on the nodes of the POG) are checked against device count constraints. Block stretching is then used to adjust the area where necessary.
It is a rough estimate as area may depend on the floorplan of the component. , it is composed of sub-blocks, the estimate is evaluated as the sum of its children's estimates. Block Adjacency Affinity: Describes the affinity of a block to its neighbourhood. It is evaluated from the product of the rough area estimate and communication density. The object attributes are involved in a wide range of heuristics including those related to the creation of an RACG, where much of the concern is on the use of graph transformation techniques based upon the use of passthrough and wiring-blocks.
An Artificial Intelligence Approach to Integrated Circuit Floorplanning by Marwan A. Jabri